AD810AR-EBZ【PDF 1/8 页】BOARD EVAL FOR AD810AR

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Evaluation Board User Guide

UG-101

One Technology Way ? P.O. Box 9106 ? Norwood, MA 02062-9106, U.S.A. ? Tel: 781.329.4700 ? Fax: 781.461.3113 ? www.analog.com

Evaluation Board for Single, High Speed Op Amps

Offered in 8-Lead SOIC Packages

FEATURES

Enables quick breadboarding/prototyping

User-defined circuit configuration

Edge-mounted SMA connector provisions

Easy connection to test equipment and other circuits

RoHS compliant

GENERAL DESCRIPTION

The Analog Devices, Inc., 8-lead SOIC evaluation board is

designed to help users evaluate single, high speed op amps

offered in 8-lead SOIC packages. The evaluation board is a bare

board (that is, there are no components or amplifier soldered to

the board, these must be ordered separately) that enables users

to quickly prototype a variety of single op amp circuits, which

minimizes risk and reduces time to market.

The evaluation board is a 2-layer printed circuit board (PCB) that

accepts SMA edge-mounted connectors on the inputs and outputs

for efficient connection to test equipment or other circuitry. The

evaluation board is designed to work with almost any of the Analog

Devices op amps offered in an 8-lead SOIC package. The evaluation

board can accommodate amplifiers that feature a power-down or

disable pin. The board can also be used with op amps that feature

external frequency compensation capacitors, such as the AD8021AR.

Figure 1 shows the component side of the bare evaluation board,

and Figure 2 shows the circuit side of the bare evaluation board.

The ground plane, component placement, and supply bypassing

have been designed to provide maximum flexibility while

minimizing parasitic inductances and capacitances. The components

of the evaluation board are primarily SMT 1206 case size, with

the exception of the electrolytic bypass capacitors (C1, C4), which

are 3528 case size.

Figure 3 shows the evaluation board schematic. The assembly

drawings are shown in Figure 4 and Figure 6. The recommended

layout patterns for making connections to the op amp and

supporting circuitry are shown in Figure 5 and Figure 7.

Two options for supply bypassing include the following:

1. Connect additional shunt capacitors (C2, C5) in parallel with

the electrolytic capacitors (C1, C4) from each supply to

ground. This technique of power supply bypassing provides

wideband rejection of unwanted noise on the supply lines. It

is implemented by placing a 0 ? resistor in the C6 position

and shunt capacitors in the C1, C2, C4, and C5 positions.

2. Connect a capacitor between the supply rails. This method

uses fewer components and can improve the PSRR at higher

frequencies but does not provide shunt bypassing to the

negative supply rail. It is implemented by inserting a 0 ?

resistor in the C2 position, then inserting the bypass capacitor

in the C5 position, and omitting C6. Optimal bypassing is

circuit dependent and, therefore, must be evaluated by the

designer for each application.

EVALUATION BOARD COMPONENT AND CIRCUIT SIDES

NOTES

1. THE EVALUATION BOARD SILKSCREEN PART NUMBER LABELING

ON THE BOARD MAY BE DIFFERENT FROM WHAT IS SHOWN HERE.

Figure 1. Component Side of Evaluation Board

PLEASE SEE THE LAST PAGE FOR AN IMPORTANT

WARNING AND LEGAL TERMS AND CONDITIONS.

Rev. A | Page 1 of 8

NOTES

1. THE EVALUATION BOARD SILKSCREEN PART NUMBER LABELING

ON THE BOARD MAY BE DIFFERENT FROM WHAT IS SHOWN HERE.

Figure 2. Circuit Side of Evaluation Board

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